The present invention relates to a turbo encoder, turbo decoder for receiving, error-correcting and decoding encoded data, and a radio base station which includes the turbo encoder and turbo decoder.
In radio communications of the next generation, communications are to be performed using turbo codes for providing noise immunity such as randomness and burstability.
The turbo encoding involves convolutional encoding data Xs to generate a sequence of packets (data sequence) X1, . . . , Xn, reordering the data Xs in accordance with a predetermined rule defined by 3GPP2 C.S0024 Version 2.0 cdma2000 High Rate Packet Data Air Interface Specification, pp9-43˜44, Oct. 27, 2000 (hereinafter abbreviated as “Document 1”) to generate data Ys, convolutional encoding the data Ys to generate another sequence of packets (data sequence) Y1, . . . Ym, and transmitting/receiving (encoding/decoding) these sequences of packets for communication. The conversion of the order in which the data sequence is arranged is called “interleaving,” and the reverse conversion is called “deinterleaving.”
Document 1 shows an approach for the interleaving, wherein FIG. 9.2.1.3.4.2.3-1 defines a method of generating, correcting or recalculating addresses of a memory at which data is written/read for interleaving. For example, assuming that a data sequence has N (bits), the data sequence except for tail bits has N′ (bits), and the data sequence N′ (=250) is interleaved, sequential addresses from 0 to 249 are issued by a counter, and the sequence of data is written into the memory one by one at the addresses. However, in the provision of Document 1, a special method is used to calculate random read addresses of the memory for increasing the randomness in order to secure the noise immunity. Since this calculation method may calculate addresses at which no data exists on the memory such as 251, 252, Document 1 also involves correction or recalculation of calculated addresses.
Therefore, for implementing the address generator, an address correction capability must be provided to regenerate read addresses of the memory from which data are read. Such address regeneration processing causes a complicated feature for generating addresses, additional processing time, and a larger processing delay in a turbo decoder.
Generally, for designing a specific address generator as mentioned above including a function of correcting generated addresses, corrected read addresses are previously listed in a table to provide a read address calculated in accordance with Document 1 and a correct read address by referencing and the table. For example, a technique described in JP-A-2001-53624 (hereinafter abbreviated as “Document 2”) employs a method of storing data write/read addresses of an interleaver/deinterleaver in a memory.
A turbo decoder described in Document 2 must have interleave read addresses or deinterleave write addresses in a memory. Also, since a plurality of data sequences must be provided corresponding to data transmission rates depending on communication conditions, a required capacity of memory is increased. For example, when a data sequence N of a packet is 256 (N=256), a memory having a capacity of 2048 bits (8×256) is required. Generally, current communication systems provide a plurality of data sequences corresponding to data transmission rates, and select a data sequence corresponding to a transmission rate in accordance with a particular communication condition. Such a communication system requires a memory capacity of 4608 (9×512) bits when the data sequence N is 512 (N=512); 10240 bits (10×1024) when the data sequence N is 1024 (N=1024); 22528 (11×2048) bits when the data sequence N is 2048 (N=2048); and 49152 (12×4096) bits when the data sequence N is 4096 (N=4096). Specifically, if a conventional decoder is designed to support all the data sequences N=256, 512, 1024, 2048, 4096, a required memory capacity sums up to 88576 bits. This results in a significant increase in circuit size and larger power consumption.